The present invention relates generally to a cache memory of a computer system, and more specifically, to dynamic partial blocking of a cache error-correcting code (ECC) checking and correcting bypass.
A cache is a memory component of a computer system that transparently retains data elements (or simply data) so that future requests for any retained data can be served faster. A data element that is stored within a cache corresponds to a pre-defined storage location within a computer memory system. Such data element might have a value that has recently been computed or be a duplicate copy of a data value that is stored in the pre-defined storage location. If requested data is contained in the cache, this is referred to as a cache hit and the request can be served by simply reading the cache. If the requested data is not contained in the cache, this is referred to as a cache miss and the data has to be fetched from system memory (or other storage medium) which is not necessarily close to the requester, and thus is comparatively slower when compared to accessing data in a cache. In general, the greater the number of requests that can be served from the cache, the faster the overall system performance becomes.
To ensure the validity of data in the cache, the data can be checked for errors. ECC bits are often kept with data in caches in order to protect against both soft and hard failures. Performing ECC processing in-line with every cache access comes with a latency penalty when returning data to the requester.